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[Other resource] multi4

Description: fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
Platform: | Size: 1516 | Author: 杨奎元 | Hits:

[Other resource] CHENGFAQI

Description: 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary -
Platform: | Size: 980 | Author: 朱冬梅 | Hits:

[Books] 一个并行高速乘法器芯片的设计与实现

Description: 一个并行高速乘法器芯片的设计与实现-a parallel high-speed chip Multiplier Design and Implementation of
Platform: | Size: 32768 | Author: 虞亮 | Hits:

[VHDL-FPGA-Verilog] multi4

Description: fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[VHDL-FPGA-Verilog] CHENGFAQI

Description: 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary-
Platform: | Size: 1024 | Author: 朱冬梅 | Hits:

[VHDL-FPGA-Verilog] bmul32

Description: 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用-Use VHDL to write a 32-bit parallel multiplier source code, has already been verified, you can directly use
Platform: | Size: 1024 | Author: zh | Hits:

[VHDL-FPGA-Verilog] bmul32_test

Description: 32位并行乘法器的测试文件，已经经过验证，可以直接使用-32-bit parallel multiplier test paper has been verified, you can directly use
Platform: | Size: 1024 | Author: zh | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] ex

Description: 用HDPLD实现的高速并行乘法器，其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
Platform: | Size: 40960 | Author: 庞永亮 | Hits:

[Other] Parallel_Booth_Multiplier

Description: Parallel Booth Multiplier Circuit in VHDL
Platform: | Size: 11264 | Author: Carlos H Nacer | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: 潘明海　刘英哲　于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: | Size: 128000 | Author: culun | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[Industry research] ADSP-21262

Description: High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)-High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)
Platform: | Size: 507904 | Author: ak | Hits:

[Software Engineering] guangshanweiyiceiangkongzhixitong

Description: 精密工作台的光栅位移测量和控制系统 精密工作台的光栅定位测量和控制系统的设计 介绍了 国内外现状和光栅检测的历史。当今采用的原理和总体方案，放大整形、5倍频电阻链细分并联4细分辨向电路，24位可逆计数器 -Grating displacement precision stage control system for precision measurements and positioning table of the raster measurement, and control system introduced in this paper the historical status and grating detection. The principle used today and the overall program, to enlarge Plastic, 5 sub-parallel multiplier resistor chain circuit 4 subdivision, 24-bit reversible counter
Platform: | Size: 137216 | Author: 于小微 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operations, but also to complete the sub-word parallel operation mode, that is, four 16bit* 16bit multiplication operation.
Platform: | Size: 99328 | Author: 余娅 | Hits:

[VHDL-FPGA-Verilog] PARALLEL-MULTIPLIER

Description: vhdl code for a 32 bit parallel multiplier
Platform: | Size: 7168 | Author: sandeep kumar | Hits:

[VHDL-FPGA-Verilog] 4MUL

Description: 四位并行乘法器的VHDL源代码，已通过验证，可以使用-Four parallel multiplier VHDL source code has been validated, you can use
Platform: | Size: 5120 | Author: 周三强 | Hits:

[VHDL-FPGA-Verilog] 16-parallel-multiplier

Description: 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
Platform: | Size: 2048 | Author: 陈俊辉 | Hits:

[MiddleWare] Serial-parallel-multiplier-verilog-design

Description: Serial parallel multiplier verilog design source code
Platform: | Size: 27648 | Author: dorababugfree | Hits:

[VHDL-FPGA-Verilog] 16-bit-parallel-mult

Description: 16位并行乘法器， 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
Platform: | Size: 2621440 | Author: 马原 | Hits:
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